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| 数字电子钟的设计 | |
| 引用本文： | 赵淑范 于秀霞. 数字电子钟的设计[J]. 长春大学学报, 1999, 9(2): 15-17 |
| 作者姓名： | 赵淑范 于秀霞 |
| 作者单位： | 长春大学电子工程学院,长春 |
| 摘 要： | 本文较系统地提出了用中小规模的７４ＬＳ系列（双列直插式）组件实现所选定的电路。进行了各单元设计，总体调试。 |
| 关 键 词： | 石英晶振器 分频器 计数器 数字电子钟 集成电路 |
Design of Digital Electronic Clock |
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| Zhao Shufan Yu Xiuxia Zhang Lingxia College of Electronics Egnineering,Chungchun University,Changchun. Design of Digital Electronic Clock[J]. Journal of Changchun University, 1999, 9(2): 15-17 | |
| Authors: | Zhao Shufan Yu Xiuxia Zhang Lingxia College of Electronics Egnineering Chungchun University Changchun |
| Affiliation: | Zhao Shufan Yu Xiuxia Zhang Lingxia College of Electronics Egnineering,Chungchun University,Changchun 130022 |
| Abstract: | The paper systematically poses how to utilize medium and small scale 74LS serious (double-row plug in)component to realize the selected circuit.Each unit was designed and the overall adjustment was performed. |
| Keywords: | silicon crystal oscillator frequency divider number counter decipherer demonstrator calibrate circuit. |
| 本文献已被 CNKI 维普 等数据库收录！ | |