| 一种新型高速高分辨率采样保持电路 |
| |
| 引用本文： | 陈红卫,吴建辉. 一种新型高速高分辨率采样保持电路[J]. 应用科学学报, 2005, 23(3): 274-277 |
| |
| 作者姓名： | 陈红卫 吴建辉 |
| |
| 作者单位： | 东南大学电子工程系, 江苏南京 210096 |
| |
| 基金项目： | 国家863计划资助项目(2002AA1Z1230) |
| |
| 摘 要： | 提出了一种新型的基于运算放大器的开关电容采样保持电路结构.采用速度补偿解决了高速高分辨采样保持电路对放大器要求增益高和速度快之间的矛盾.具体设计了采样保持电路,特别设计了其中的快速时间连续电压比较器.用Chart 0.35μm CMOS工艺,进行HSPICE仿真,结果表明,本文设计的采样保持电路的分辨率为10位,采样速率高于70 MHz/s.
|
| 关 键 词： | 运算放大器 采样保持 模数转换器 |
| 文章编号： | 0255-8297(2005)03-0274-04 |
| 收稿时间： | 2004-03-12 |
| 修稿时间： | 2004-05-08 |
A New High-Speed and High-Resolution Sample-and-Hold Circuit |
| |
| CHEN Hong-wei,WU Jian-hui. A New High-Speed and High-Resolution Sample-and-Hold Circuit[J]. Journal of Applied Sciences, 2005, 23(3): 274-277 |
| |
| Authors: | CHEN Hong-wei WU Jian-hui |
| |
| Affiliation: | Department of Electronic Engineering, Southeast University, Nanjing 210096, China |
| |
| Abstract: | A new sample-and-hold circuit based on an operational amplifier is described in this paper.It is useful to solve the conflict between speed and DC gain of an amplifier in a high-speed and high-resolution sample-and-hold circuit by using a speed compensation circuit.The circuit was simulated by 0.35 μm CMOS technology.The sample rate is higher than 70 MHz per second and the resolution is 10 bits. |
| |
| Keywords: | analog-to-digital converter Op Amp sample-and-hold |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
| 点击此处可从《应用科学学报》浏览原始摘要信息 |
|
点击此处可从《应用科学学报》下载全文 |
