顶层进位级联CLA的算法与设计规则

提出了一种新型加法器结构——顶层进位级联超前进位加法器，该结构将超前进位加法器(CLA)底层进位改为顶层超前进位单元进位．给出了顶层进位级联超前进位加法器延迟时间公式．推导出该结构模块延迟时间公式、最大级联数Km(max)、最优分组方案等重要结果，并归纳出优化设计规则．

Algorithm of TC2CLA (Top-level Carry Cascade Carry Lookahead Adders) and its design rule

The structure of Carry Lookahead Adder (CLA) replaced bottom level carry cascade with top level LAC (Look Ahead Carry) carry cascade among modules. The propagation delay time of the highest bit carry was reduced by K m(m-1)t pd and maximum delay time of the highest bit sum by K m(m-1)t pd . Resource expense and power dissipation were fixed. The delay time formulae of TC 2CLA were given based on the standard delayed model of logic gate and optimum circuit unit. The sense of all teams in the formulae was expounded. The delay time formulae of the module of TC 2CLA, the maximum cascade number K m (max) , the optimum layout of grouping and the above results were deducted. The optimum design rule of TC 2CLA was inducted from power dissipation and area constraint reflected by maximum fanin and fanout and speed constraint. The designed 32?bit TC 2CLA showed a maximum of 6 fanouts and a critical path with logic depth of 4.