Recent Advance in Non-Krylov Subspace Model Order Reduction of Interconnect Circuits

Model order reduction of interconnect circuits is an important technique to reduce the circuit complexity and improve the efficiency of post-layout verification process in the nanometer VLSI design. Existing works using the Krylov subspace method are very efficient, but the resulting models are less compact and lack global accuracy. Also, existing methods cannot handle interconnect circuits with large input and output ports. Recent advances in reduction techniques using non-Krylov subspace techniques such a...