| 基于FPGA的高分辨率贝尔CFA插值算法的设计与实现 |
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| 引用本文： | 张向飞,张刚,程永强.基于FPGA的高分辨率贝尔CFA插值算法的设计与实现[J].太原理工大学学报,2006(Z1). |
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| 作者姓名： | 张向飞 张刚 程永强 |
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| 作者单位： | 太原理工大学信息工程学院 山西太原030024 |
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| 基金项目： | 国家自然科学基金资助项目(60372058)，山西省自然科学基金资助项目(20051009) |
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| 摘 要： | 实现了基于FPGA的双线性CFA插值算法。该算法的处理对象是每个像素为8 bit的XGA@15 Hz的Bayer模板数据,目的是能得到每个像素是24 bit的XGA@15 Hz的彩色图像数据。输入的数据先进入缓存模块,缓存模块是由FPGA内部的双口的RAM构成,从缓存中输出的数据被分成奇行组和偶行组,然后奇行组的数据经选择器进入奇行奇列运算块和奇行偶列运算块,偶行组的数据经选择器进入偶行奇列运算块和偶行偶列运算块,最后在插值控制模块的作用下,各运算块处理的数据经输出选择器输出。
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| 关 键 词： | FPGA VHDL CFA插值 实时 高分辨率 |
The Designing and Realization of High-resolution Bayer CFA Interpolation Algorithm Based on FPGA |
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| ZHANG Xiang-fei,ZHANG Gang,CHENG Yong-qiang.The Designing and Realization of High-resolution Bayer CFA Interpolation Algorithm Based on FPGA[J].Journal of Taiyuan University of Technology,2006(Z1). |
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| Authors: | ZHANG Xiang-fei ZHANG Gang CHENG Yong-qiang |
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| Abstract: | This paper implemented a bilinear CFA interpolation algorithm based on FPGA.The processing object of the algorithm is Bayer module data of 8bit per-pixel XGA@15 Hz.The goal of this research is to gain color image data of 24bit per-pixel XGA@15 Hz.Input data enter into cache module,the cache module is made of inner dual-port RAM block of FPGA,the output data from cache is divided into odd-row-group and even-row-group,secondly,the data of odd-row-group enter into the odd-row-odd-column operation block and the odd-row-even-column operation block,and the data of even-row-group enter into the even-row-odd-column operation block and the even-row-even-column operation block,finally,under the action of the interpolation controlling module,the data of each operation block processed arrive exterior though output multiplexer. |
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| Keywords: | FPGA VHDL CFA interpolation Real-time High-resolution |
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