一种高速缓冲存储器的可综合伪随机功能验证方法

针对微处理器的高速缓冲存储器（Cache），提出了一种可综合的伪随机功能验证方法，对其在实际芯片中的性能进行测试，并与常见的基于软件模拟的随机功能验证方法进行了对比.结果表明，与基于软件模拟的伪随机功能验证方法相比，所提出的可综合伪随机验证方法的处理速度快约3个数量级，并且能够发现更多的功能错误.

A Synthesizable Pseudo-Random Functional Verification Method for Cache

For the Cache in the microprocessors, a synthesizable pseudo-random functional verification method was proposed. This method was applied in the real chips, and was compared with the pseudo-random verification method on software simulation in performance. The results show that the method is faster by about three orders of magnitude, and can find more bugs in the designs in comparison to the pseudo-random verification method on software simulation.