| JTAG软核设计与仿真 |
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| 引用本文： | 吕彩霞,李哲英. JTAG软核设计与仿真[J]. 北京联合大学学报(自然科学版), 2007, 21(2): 58-62 |
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| 作者姓名： | 吕彩霞 李哲英 |
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| 作者单位： | 北京交通大学,电子信息工程学院,北京,100044;北京联合大学,信息学院,北京,100101 |
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| 基金项目： | 北京市教委科技强教拔尖人才项目 |
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| 摘 要： | 硬件系统的规模越来越大,复杂度越来越来高,对其进行测试也越来越困难,JTAG边界扫描技术较好地解决了传统测试的不足,边界扫描测试是一种新型的VLSI电路测试及可测试性设计方法。JTAG是符合IEEE规范的测试技术,JTAG的设计实现了测试复杂度的降低,适合进行大规模集成电路的测试。论述边界扫描技术的结构特征及软核设计方法的同时,分析了JTAG电路中数据传输的路径及电路对速度的影响,并以采样指令为例进行了功能仿真。
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| 关 键 词： | JTAG 边界扫描 逻辑仿真 大规模集成电路 |
| 文章编号： | 1005-0310（2007）02-0058-05 |
| 收稿时间： | 2006-05-10 |
| 修稿时间： | 2006-05-10 |
JTAG Soft Core Define and Emulation |
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| LV Cai-xia,LI Zhe-ying. JTAG Soft Core Define and Emulation[J]. Journal of Beijing Union University, 2007, 21(2): 58-62 |
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| Authors: | LV Cai-xia LI Zhe-ying |
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| Affiliation: | 1. School of Electronics and Engineering, Beijing JiaoTong University, Beijing 100044, China; 2. Information College of Beijing Union University, Beijing 100101, China |
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| Abstract: | As the scale and complexity of hardware systems increased quickly,it is now more difficult to test them.The JTAG boundary scan technology can well make up the shortcoming of traditional test technology.Boundary-scan technology is a new and effective way of test and design-for-testability for VLSI circuits.JTAG is the test technology of IEEE specification.Its implementation reduces the complexity of the testing and is suitable for VLSI testing.The boundary-scan,the configuration character and soft core design methods are introduced.It also analyzes the route of data transfers and effects on speed in JTAG circuit,and emulated via a sampling instruction. |
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| Keywords: | JTAG boundary-scan soft core VLSI |
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