Design and simulation of a Torus topology for network on chip

Aiming at the applications of NOC (network on chip) technology in rising scale and complexity on chipsystems, a Torus structure and corresponding route algorithm for NOC is proposed. This Torus structure improvestraditional Torus topology and redefines the denotations of the routers. Through redefining the router denotationsand changing the original router locations, the Torus structure for NOC application is reconstructed. On the basisof this structure, a dead-lock and live-lock free route algorithm is designed according to dimension increase. SystemC is used to implement this structure and the route algorithm is simulated. In the four different traffic patterns, average, hotspot 13%, hotspot 67% and transpose, the average delay and normalization throughput of this Torusstructure are evaluated. Then, the performance of delay and throughput between this Torus and Mesh structure iscompared. The results indicate that this Torus structure is more suitable for NOC applications.