| 一种减少金属层数的芯片物理设计方法 |
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| 引用本文： | 刘金禾,林平分.一种减少金属层数的芯片物理设计方法[J].科技信息,2012(11):66-66,18. |
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| 作者姓名： | 刘金禾 林平分 |
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| 作者单位： | 北京工业大学北京市嵌入式系统重点实验室,中国北京100124 |
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| 摘 要： | 数字后端物理版图设计是整个芯片设计的关键一步,而减少设计时所用的金属层数是IC行业中缩减芯片成本的一个重要措施。本文以SMIC0.18μm工艺下一款SmartCard芯片的实际设计方案为例,首先分析了金属层数与成本的关系,之后分析其可行性,并提出了具体的布局布线方案,最终以成功的流片结果论证了该减少金属层数设计方案的可行性。
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| 关 键 词： | IC数字后端 金属层数 版图设计 |
A Method of Chip Physical Design with Reduced Metal Layers |
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| LIU Jin-he,LIN Ping-fen.A Method of Chip Physical Design with Reduced Metal Layers[J].Science,2012(11):66-66,18. |
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| Authors: | LIU Jin-he LIN Ping-fen |
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| Institution: | (Beijing University of Technology, Beijing Embedded System Key Lab, Beijing, 100124, China) |
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| Abstract: | Digital backend layout design is a key step in the whole chip design, and one of the important measures to cut the chip cost is reducing metal layers in the design. Based on the design of a smartcard chip in SMIC 0.18μm technology, this paper analyzed the relation between metal layers and cost, and the feasibility of reducing metal layers, then put forward a design scheme. Finally, the results of successful tapeout proved the feasibility of this scheme. |
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| Keywords: | IC digital backend Metal layer Layout design |
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