| 基于PCI总线的边界扫描主控器的FPGA设计与实现 |
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| 引用本文： | 朱华贵,何光普,陈光(礻禹). 基于PCI总线的边界扫描主控器的FPGA设计与实现[J]. 四川师范大学学报(自然科学版), 2005, 28(4): 501-504 |
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| 作者姓名： | 朱华贵 何光普 陈光(礻禹) |
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| 作者单位： | 江西财经大学,电子学院,江西,南昌,330013;电子科技大学,自动化工程学院,四川,成都,610054;电子科技大学,自动化工程学院,四川,成都,610054;乐山师范学院,物理与电子信息科学系,四川,乐山,614004;电子科技大学,自动化工程学院,四川,成都,610054 |
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| 基金项目： | 国家自然科学基金资助项目（60372001） |
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| 摘 要： | 在分析边界扫描测试技术的工作机制对测试主控系统的功能需求基础上,提出了一种基于PCI总线采用FPGA实现的低成本边界扫描测试主控器的硬件设计方案.该系统以PC机为平台,利用FPGA器件设计实现JTAG主控芯核,并在主控器芯核内加入FIFO,提高了PCI总线的传送速率,使用户能够利用计算机方便的组成一个边界扫描测试系统.经仿真和测试实践表明,该系统产生的测试信号完全满足IEEE1149.1协议的时序要求,对支持IEEE1149.1协议的芯片进行功能测试和PCB板的互连测试及电路故障诊断.该系统结构简单,使用方便,工作可靠.
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| 关 键 词： | JTAG 边界扫描 FPGA PCI 测试系统 |
| 文章编号： | 1001-8395（2005）04-0501-04 |
| 收稿时间： | 2004-10-29 |
| 修稿时间： | 2004-10-29 |
FPGA Design and Realization of the Boundary Scan Master Controller Based on PCI-bus |
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| ZHU Hua-gui,HE Guang-pu,CHEN Guang-ju. FPGA Design and Realization of the Boundary Scan Master Controller Based on PCI-bus[J]. Journal of Sichuan Normal University(Natural Science), 2005, 28(4): 501-504 |
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| Authors: | ZHU Hua-gui HE Guang-pu CHEN Guang-ju |
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| Abstract: | Reviewing the test mechanism of boundary-scan and the functional requirement of boundary-scan tester, this paper presents a hard-ware design project based on PCI-bus boundary-scan master controller by using FPGA. In the system, PC works as a platform, the design adopts FPGA for JTAG IP core and adds FIFO for accelerating the rate in transmission data, so the system is characterized by the whole function, and has a low price. Simulation and practical test results show that the system is feasible, the performance of the test system meets the requirements of IEEE 1149.1. It can be used in the boundary-scan test of IC and PCB, as well as in the chip level integrated circuit of function test and fault modeling. The system has a simple structure, and it is convenient and reliable in use. |
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| Keywords: | JTAG Boundary-Scan FPGA PCI Test system |
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