基于FPGA的高速FFT处理器的设计与实现

针对高速实时信号处理的要求，提出了4096点快速傅立叶变换（FFT）处理器在现场可编程门阵列（FPGA）中的设计与实现方法。该方法采用了按频率抽取（DIF）基4算法和6级流水线结构，每级均采用FIFO存储器实现延迟功能，和四路转接器一起共同完成序列的码位抽取。为了避免数据溢出，采用块浮点结构来表示数据，节省了器件资源。实验结果表明，该方法在保证运算精度和实现复杂度的同时，提高了处理器的数据时钟频率和处理速度。

Design and Implementation of High Speed FFT Processor with FPGA

To meet the requirement of high data processing, an implementation method of 4 096 points high rate FFT processor in FPGA was discussed. Based on decimate in frequency (DIF) Radix-4 algorithm, a 6 levels pipeline structure was adopted. In each level, FIFO was used to delay sequence and it coupled with 4-road commutator was employed to change the sequence of address. To balance the precision and the speed, the block floating point operation was adopted. Experimental results show that under prerequisite of accuracy and complexity, the method improves the operating clock and processing rate.