首页 | 本学科首页   官方微博 | 高级检索  
     检索      

基于FPGA快速二维DCT图像编码结构
引用本文:龙飞,李良荣,李绪诚.基于FPGA快速二维DCT图像编码结构[J].贵州大学学报(自然科学版),2012,29(4):67-70.
作者姓名:龙飞  李良荣  李绪诚
作者单位:1. 贵州民族大学计算机与信息科学学院,贵州贵阳,550025
2. 贵州大学理学院,贵州贵阳,550025
基金项目:贵州省科学基金项目,贵州大学青年基金项目
摘    要:本文提出了一种二维DCT快速算法的FPGA实现结构,采用行列分解算法将二维DCT分解成两个一维DCT和一个转置缓冲器组成的结构,其中一维DCT借鉴Arai DCT算法,并采取了FPGA特有的并行的流水线技术,该结构极大减少了加法器和乘法器的数量,节省了计算时间。该结构的特点是高数据吞吐率、硬件资源消耗少,功耗低。实验结果证明了二维DCT核设计的正确性,适合图像的实时处理。

关 键 词:二维离散余弦变换(DCT)  流水线结构  硬件结构  现场可编程门阵列(FPGA)

FPGA Rapid Two-dimensional DCT Image Coding Structure
LONG Fei , LI Liang-rong , LI Xu-cheng.FPGA Rapid Two-dimensional DCT Image Coding Structure[J].Journal of Guizhou University(Natural Science),2012,29(4):67-70.
Authors:LONG Fei  LI Liang-rong  LI Xu-cheng
Institution:( School of Computer and Information Engineering, Guizhou University for Nationalities, Guiyang 550025 2. College of Science, Guizhou University, Guiyang,550025 ,China)
Abstract:In this paper, a two-dimensional DCT fast algorithm for FPGA implementation structure. Decomposition algorithm using the line-column, 2D-DCT is broken down into the structure of two 1D-DCT and a transpose buffer, and 1 D-DCT is learn from Arai DCT algorithm, and mining is indeed a unique parallel pipeline technique in FPGA. The structure greatly reduces the adder and multiplier is the number, to save calculation time. The structure is characterized by high data throughput, the hardware resource consumption, low power consumption. The experimental results show the correctness of the two-dimensional DCT core design, suitable for real-time processing of the image.
Keywords:DCT  pipelined architecture  hardware structure  FPGA
本文献已被 CNKI 维普 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号