高锁定范围半盲型过采样时钟数据恢复电路设计

采用标准0.18 μm CMOS工艺,设计了一种高锁定范围的半盲型过采样时钟数据恢复电路.该时钟数据恢复电路（Clock and Data Recovery,CDR）主要由鉴频器（Frequency detector,FD）、多路平行过采样电路、10位数模转换器（Digital To Analog Converter,DAC）、低通滤波器（Low Pass Filter,LPF）、多相位压控振荡器（Voltage Controlled Oscillator,VCO）等构成.该CDR电路采用模数混合设计方法,并提出了基于双环结构实现对采样时钟先粗调后微调的方法,并且在细调过程中提出了加权调相的方法缩短采样时间.仿真结果表明,该CDR电路能恢复1.25～4.00 Gbps之间的伪随机数据电路,锁定时间为2.1 μs,VCO输出的抖动为47.12 ps.

High Locking Range Semi-Blind Oversampling Clock and Data Recovery Circuit

Based on SMIC 0.18 μm CMOS process, a semi-blind oversampling clock data recovery circuit with a high locking range is designed. This clock and data recovery （CDR） is mainly composed by the frequency detector, multiple parallel oversampling circuit, 10 bit digital analog converter （DAC）, low pass filter（ LPF）, multi-phase voltage controlled oscillator（VCO）. The mixed-signal technique is used in the CDR. The sampling clock can be fine adjusted after the coarse adjustment by bicyclic structure. The circuit adjusts the phase with the weighting method in the process of fine tuning to make the circuit more quickly locked. Simulation results show that the CDR circuit can recover the NRZ data from 1.25 Gbps to 4.00 Gbps, the CDR is locked at 2.1 μs and the jitter of recoverd clock is 47.12 ps.