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基于树状图的波形数字滤波器拓扑结构优化方法
引用本文:薛丞博,马越,任仕伟. 基于树状图的波形数字滤波器拓扑结构优化方法[J]. 北京理工大学学报, 2018, 38(5): 505-510. DOI: 10.15918/j.tbit1001-0645.2018.05.011
作者姓名:薛丞博  马越  任仕伟
作者单位:北京理工大学 信息与电子学院,北京,100081;北京理工大学 信息与电子学院,北京,100081;北京理工大学 信息与电子学院,北京,100081
基金项目:国家自然科学基金资助项目(61271113)
摘    要:针对常规波形数字滤波器(wave digital filter,WDF)拓扑结构表达效率低下、结构易混乱的问题,本文利用适配器的可拆分性,提出基于WDF二叉树的拓扑结构表达方法,使等效电路结构清晰直观,从WDF二叉树的形态可迅速获知等效电路的模块并行度、最长路径等关键信息.此外,本文结合WDF端口适配器的端口对称性,进一步提出WDF二叉树的优化方法.通过对满足要求的结点及附属子叶进行位置交换,令二叉树更为扁平、缩短"入射-反射"过程的最大路径长度,使WDF-FPGA仿真系统的模块并行度和仿真速度得到提升.电路仿真模型优化后的反射步长减少42.86%、入射步长减少38.9%,总运算时间降至0.366 ms. 

关 键 词:波形数字滤波器  电路仿真  FPGA  拓扑优化  二叉树
收稿时间:2017-08-02

A Topology Optimization Method of Waveform Digital Filter Based on Dendrogram
XUE Cheng-bo,MA Yue and REN Shi-wei. A Topology Optimization Method of Waveform Digital Filter Based on Dendrogram[J]. Journal of Beijing Institute of Technology(Natural Science Edition), 2018, 38(5): 505-510. DOI: 10.15918/j.tbit1001-0645.2018.05.011
Authors:XUE Cheng-bo  MA Yue  REN Shi-wei
Affiliation:School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China
Abstract:In this paper,an optimizing methodology for wave digital filter (WDF)equivalent circuit was proposed.This binary tree based method can simplify simulation system and improve system performance on speed.The WDF with binary tree representation was provided with a clear and intuitive structure to solve the low expressing efficiency issue in traditional WDF topology.The shape of this tree can directly indicate essential information of WDF equivalent circuit,such as module parallelism and the longest path. Moreover, considering the port symmetry of the WDF adapter,an optimizing methodology was presented for WDF binary tree to reduce processing steps in each simulating cycle and improve the overall performance of simulation.The optimization results show that, the reflection step length can be reduced by 42.86%,while the incidence step length can be reduced by 38.9%,the total operation time can be reduced to 0.3 6 6 ms.
Keywords:wave digital filter  analog circuit simulation  FPGA  topology optimization  binary tree
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