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| 应用输入向量约束的门替换方法缓解电路老化 | |
| 引用本文： | 李扬,梁华国,陶志勇. 应用输入向量约束的门替换方法缓解电路老化[J]. 应用科学学报, 2013, 31(5): 537-543. DOI: 10.3969/j.issn.0255-8297.2013.05.015 |
| 作者姓名： | 李扬 梁华国 陶志勇 |
| 作者单位： | 1. 合肥工业大学计算机与信息学院，合肥2300092. 江苏商贸职业学院信息系，江苏南通2260003. 合肥工业大学电子科学与应用物理学院，合肥230009 |
| 基金项目： | 国家自然科学基金(No. 61274036, No.61371025, No.61300212, No.61306049)；教育部博士点基金(No. 20110111120012)；江苏省高校“青蓝工程”项目基金(No. 2010121312)资助 |
| 摘 要： | 为缓解负偏置温度不稳定性(negative bias temperature instability, NBTI) 效应引起的电路老化，提高电路可靠性，提出一种在电路待机状态下应用输入向量约束的门替换方法. 运用动态和静态的NBTI 模型进行感知NBTI 的静态时序分析，确定潜在关键路径，考虑路径相关性的关键门算法以确定关键门，并生成能使关键门 最大限度处于恢复阶段的输入向量. 对输入向量无法控制的关键门采用门替换方法进行内部控制. 对ISCAS 标准电路的实验结果表明，电路时序余量为5% 时，该方法的平均门替换率降低到9.68%，时延改善率提高到39.65%. |
| 关 键 词： | 电路老化 NBTI 输入向量 门替换 |
| 收稿时间： | 2012-12-25 |
| 修稿时间： | 2013-06-22 |
Gate Replacement with Input Vector Constraint to Mitigate Circuit Aging |
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| LI Yang,LIANG Hua-guo,TAO Zhi-yong. Gate Replacement with Input Vector Constraint to Mitigate Circuit Aging[J]. Journal of Applied Sciences, 2013, 31(5): 537-543. DOI: 10.3969/j.issn.0255-8297.2013.05.015 | |
| Authors: | LI Yang LIANG Hua-guo TAO Zhi-yong |
| Affiliation: | 1. School of Computer and Information, Hefei University of Technology, Hefei 230009, China;2. Department of Information, Jiangsu Vocational College of Business, Nantong 226000, Jiangsu Province, China;3. School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, China |
| Abstract: | To mitigate NBTI-induced circuit aging and enhance circuit reliability, gate replacement with input vector constraint during standby is proposed. The potential critical paths are found by using dynamic and static NBTI-aware static timing analysis. The critical gates are then found by considering path correlation. An input vector is generated to make the critical gates in a recovery phase to the largest extent. Gate replacement is applied to the critical gates beyond control. Experiment results with ISCAS benchmark circuit demonstrate that the average gate replacement rate is reduced to 9.68%, and the average delay improvement is increased to 39.65% with the circuit timing margin 5%. |
| Keywords: | circuit aging NBTI input vector gate replacement |
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