K—9卷积码的Viterbi译码算法及其FPGA实现

探讨了ＣＤＭＡ数字移动通信中的差错控制问题，研究用约束度Ｋ＝９的卷积编码和最大似然Ｖｉｔｅｒｂｉ译码的差错控制方案。在Ｖｉｔｅｒｂｉ译码算法中，提出了原位运算度量、保存路径转移过程和循环存取幸存路径等方法，能有效地减少存储量、降低功耗，使得Ｋ＝９的Ｖｉｔｅｒｂｉ译码算法可以单片ＸＣ４０１０ ＦＰＧＡ为主的器件上实现，其性能指标符合ＣＤ－ＭＡ数字移动通信ＩＳ－９５标准要求。文中给出了实测的算法性能，

ViterbiDecodingAlgorithmandItsFPGA Implementation for K=9 Convolutional Codes

This paper deals with the error control problem in digital mobile communications. The scheme which employs the maximum likelihood Viterbi algorithm for decoding the K=9 convolutional data is studied. In this scheme, some efficient methods such as the in place modification operation for path metrics, the saving of path transition and the circle access for path surving are presented. By using these methods, the RAM size needed for saving metrics and paths and the power consumption are decreased. It is shown that the Viterbi algorithm of K=9 whose performance specifications satify the IS 95 standard can be implemented with a single chip FPGA XC4010. The performance is tested, and the implementation consideration is discussed.