| 快速锁定的宽频带CMOS锁相环设计 |
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| 引用本文： | 雷[金監]铭,何威,邹志革,温朝晔. 快速锁定的宽频带CMOS锁相环设计[J]. 华中科技大学学报(自然科学版), 2012, 40(7): 71-74 |
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| 作者姓名： | 雷[金監]铭 何威 邹志革 温朝晔 |
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| 作者单位： | 华中科技大学电子系,湖北武汉,430074 |
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| 基金项目： | 湖北省自然科学基金资助项目，华中科技大学自主创新基金资助项目 |
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| 摘 要： | 设计了一种可快速锁定的宽频带CMOS电荷泵锁相环电路.通过增加一个自适应带宽控制模块,当锁相环处于捕捉状态时,增加环路带宽实现快速锁定;锁相环接近锁定状态时,减小带宽,保证环路的稳定性和减小杂散.同时还设计了能工作在宽频率范围的压控振荡器.该锁相环基于0.25μm CMOS工艺,供电电压为2.5V时,工作范围在960～2 560MHz,功耗为8.9～23.2mW,锁定时间小于12μs.
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| 关 键 词： | 锁相环 快速锁定 环形压控振荡器 宽频带 相位噪声 |
Design of a fast-lock CMOS phase-locked loop with wide band width |
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| Lei Jianming He Wei Zou Zhige Wen Chaoye. Design of a fast-lock CMOS phase-locked loop with wide band width[J]. JOURNAL OF HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY.NATURE SCIENCE, 2012, 40(7): 71-74 |
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| Authors: | Lei Jianming He Wei Zou Zhige Wen Chaoye |
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| Affiliation: | Lei Jianming He Wei Zou Zhige Wen Chaoye(Department of Electronic Science and Technology,Huazhong University of Science and Technology,Wuhan 430074,China) |
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| Abstract: | A Fast-lock phase-locked loop(PLL)with a wide band width was designed based on CMOS process.By adding a bandwidth-control module,a wider bandwidth was used during transient to reduce lock time.While a phase lock was attained,the bandwidth was shifted to a smaller value for optimum spectrum.A wide-range voltage-controlled oscillator(VCO)was also designed in the circuit.The PLL can operate in the frequency range from 960to 2 560MHz with a setting time of less than 12 μs,and the power dissipation is from 8.9to 23.2mW at a 2.5Vsupply. |
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| Keywords: | phase-locked loop fast lock ring voltage-controlled oscillator wide rage phase noise |
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