交织多址接入系统定点Logistic交织序列生成算法

交织多址接入(interleave division multiple access, IDMA)技术作为典型的非正交多址接入技术，受到学术界和产业界的广泛关注。为降低IDMA系统多用户检测过程存储空间和计算复杂度，采用双极性化的定点Logistic序列与待(解)交织序列对应相乘方式完成(解)交织;同时，为降低任意量化比特长度的定点Logistic序列生成过程时延，采用现场可编程逻辑门阵列进行生成。利用Logistic系统李雅普诺夫指数，确定处于混沌状态的定点Logistic序列量化比特长度;基于平衡度和互相关门限，确定定点Logistic序列开始位置和初值;采用查表法构建非对称基本乘法器，并采用移位相加法计算总乘法器。仿真结果表明，所提算法可以充分利用Logistic序列混沌、平衡度、相关等特性，具有较好的误码率性能。

Fixed-point Logistic interleaving sequence generation algorithm for interleave division multiple access system

Interleave division multiple access (IDMA) technology, as a typical non-orthogonal multiple access technology, has been widely concerned by academia and industry. In order to reduce storage space and computational complexity of the multi-user detection process of the IDMA system, a dual-polarized fixed-point Logistic sequence is multiplied with the corresponding (de-)interleaving sequence to complete the (de-)interleaving. In order to reduce the time delay in the fixed-point Logistic sequence generation process with arbitrary quantization bit accuracy, a field programmable gate array (FPGA) is used for sequence generation. Firstly, the quantization bit length of the fixed-point Logistic sequence in a chaotic state is determined by using the Lyapunov exponent of the Logistic system; then the initial value and start position of the fixed-point Logistic sequence are determined based on the equilibrium degree and cross correlation threshold; finally, the non-symmetric basic multiplier is constructed by the table look-up (LUT) method, and the total multiplier is calculated by the shift-addition method. Simulation results show that the proposed algorithm can sufficiently use the chaos, equilibrium and correlation properties of Logistic sequences and has a good bit error rate (BER) performance.