| 时序分析中时序约束条件的确立和检验算法 |
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| 引用本文： | 尹国丽,林争辉,刘彦松. 时序分析中时序约束条件的确立和检验算法[J]. 上海交通大学学报, 2003, 37(6): 809-811 |
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| 作者姓名： | 尹国丽 林争辉 刘彦松 |
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| 作者单位： | 上海交通大学,电子工程系,上海,200030 |
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| 摘 要： | 针对同步多相时序电路在满足建立时间约束时却忽视保持时间约束的情况，提出了一个基于锁存器多相时序电路的建立时间约束和保持时间约束的检验算法。该算法考虑了时钟偏斜对建立时间和保持时间的影响。经具体时序电路验证，本文检验算法是可行的。
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| 关 键 词： | 大规模集成电路 时序电路 锁存器 建立时间约束 保持时间约束 算法 |
| 文章编号： | 1006-2467(2003)06-0809-03 |
| 修稿时间： | 2002-06-19 |
The Establishment and Verification Algorithm of Timing Constraints in Timing Analysis of Integrated Circuits |
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| YIN Guo li,LIN Zheng hui,LIU Yan song. The Establishment and Verification Algorithm of Timing Constraints in Timing Analysis of Integrated Circuits[J]. Journal of Shanghai Jiaotong University, 2003, 37(6): 809-811 |
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| Authors: | YIN Guo li LIN Zheng hui LIU Yan song |
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| Abstract: | According to the case that the sequential circuits satisfy the setup time constraints while ignore the hold time constraints, this paper presented a checking algorithm which checks setup time constraints, hold time constraints of those multi phase latches based sequential circuits. It also captures the effects of clock skew on setup time and hold time, which proves feasible by a specific sequential circuit. |
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| Keywords: | large scale integrated circuits sequential circuits latches setup time constraint hold time constraint algorithms |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
