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基于国产FPGA的星载Nor Flash控制器设计与验证
引用本文:祝倩,白云飞,安军社.基于国产FPGA的星载Nor Flash控制器设计与验证[J].重庆邮电大学学报(自然科学版),2021,33(4):630-636.
作者姓名:祝倩  白云飞  安军社
作者单位:中国科学院 复杂航天系统电子信息技术国防科技创新重点实验室,北京100190;中国科学院 国家空间科学中心,北京100190;中国科学院大学,北京100190;中国科学院 复杂航天系统电子信息技术国防科技创新重点实验室,北京100190;中国科学院 国家空间科学中心,北京100190
基金项目:中国科学院火星环绕器载荷管理器项目(Y66602BC4S)
摘    要:为满足航天星载存储系统进一步提高数据传输速率和系统可靠性,降低定制成本等需求,设计了一款基于国产宇航级可编程逻辑门阵列(field programmable gata array,FPGA)的Nor Flash控制器.该控制器针对Nor Flash编程和擦除操作速度较慢等问题,采用了解锁省略策略与增设写入缓冲器编程算法协同优化提高Nor Flash控制指令效率.控制器通过Verilog HDL语言编写有限状态机实现,modelsim仿真结果表明,控制器运作正常.同时,利用ER2C-3000型国产FPGA评估板搭建片上系统(system on a chip,SoC)进行了控制器优化算法验证,在设置工程的系统时钟为10 MHz和连续写入16个字/32字节操作条件下,设计比标准编程算法速度提升约3.5倍,比硬件解锁单字编程算法速度提升约2倍.为进一步提高国产星载SoC存储系统运转效率提供了新的思路.

关 键 词:Nor  Flash控制器  FPGA  有限状态机  片上系统
收稿时间:2019/11/28 0:00:00
修稿时间:2021/5/16 0:00:00

Design and verification of onboard Nor Flash controller based on domestic FPGA
ZHU Qian,BAI Yunfei,AN Junshe.Design and verification of onboard Nor Flash controller based on domestic FPGA[J].Journal of Chongqing University of Posts and Telecommunications,2021,33(4):630-636.
Authors:ZHU Qian  BAI Yunfei  AN Junshe
Institution:Key Laboratory of Electronics and Information Technology for Space Systems, Chinese Academy of Sciences, Beijing 100190, P. R. China;National Space Sciences Center, Chinese Academy of Sciences, Beijing 100190, P. R. China;University of Chinese Academy of Science, Beijing 100190, P. R. China
Abstract:To adapt the requirements of spaceborne storage system, including further improving data transmission rate, system reliability, and reducing customization cost, a novel Nor Flash controller based on domestic astronaut-class field programmable logic gate array (FPGA) was designed. The controller utilizes the optimization method of lock elusion function and the write buffer programming algorithm to overcome the problems of slow programming and erase operation. The controller is carried out by writing the finite state machine in Verilog HDL language, and the simulation results of modelsim indicates that the revised controller works perfectly. The controller first implements on the domestic er2c-3000 FPGA evaluation board to build the system SoC. After optimizing, the speed of this design is improved by about 3.5 times compared with the standard single word programming and about 2 times compared with the hardware unlock single word programming under the operating conditions of setting the system clock as 10 MHz and continuously writing 16 words/32 bytes. This method provides a new idea for further improving the efficiency of space-borne SoC.
Keywords:Nor Flash controller  FPGA  finite state machine  system on a chip
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