一种全数字正交发射机中数字前端电路的设计

本文设计了一种应用于全数字正交发射机的数字前端电路(DFE).DFE主要由I/Q 2路插值倍数为24的高速升采样数字滤波器构成,将基带带宽为20MHz的信号从100MHz升采样至2.4GHz,同时能够有效滤除镜像信号.其中第1级滤波器采用转置结构实现,并通过对过渡带的优化而将滤波器阶数从41降低至18.后3级半带滤波器则通过结构的变换,巧妙地将插值与滤波器过程结合起来,降低了部分单元的工作频率,优化了功耗;另外,在高频部分,为了满足时序要求,对关键路径进行流水线处理,并使用低阈值管提高工作频率.此外,在DFE中还增加了低功耗的串行外设接口(SPI)可配置的预失真查找表,从而实现数字预失真(DPD)的功能,并通过对称性将查找表存储量优化17×17.DFE的总体版图面积为0.34mm2,包括时钟分频模块在内的总功耗估算为34.8mW,其中数字预失真表部分的功耗为3.5mW.仿真结果表明,本文带有预失真查找表的DFE能够将发射机的误差矢量幅度(EVM)从31.6%降低至3.26%.

Design of a Digital Front End in All-Digital Quadrature-Transmitter

A Digital-Front-End (DFE) in all-digital quadrature-transmitter is designed.The DFE consists of I/Q quadrature high speed digital filter with interpolation rate of 24,up-sampling 20 MHz baseband signal from 100 MHz to 2.4 GHz,and depressing image signal as well.The first stage filter is designed with transposed architecture,and the order of the filter is reduced from 41 to 18 after optimization of transition band.The function of interpolation and filter of the latter 3 stage filters are combined together to reduce frequency for part of the filter,thus reduce power consumption;what's more,the filter is designed with LVT MOST and the critical path is pipelined to meet the timing requirements.A low power Serial Peripheral Interface(SPI) configurable Look-Up-Table (LUT) is added in DFE to realize the function of digital pre-distortion(DPD),and it is reduced to 17 × 17 terms with symmetry principle.The total area of DFE is 0.34 mm2,and the power consumption is about 34.8 mW with clock division part included,with which the power consumption of DPD is only 3.5 mW.Simulation result indicates that,the proposed DFE can reduce EVM from 31.6％ to 3.26％ with digital pre-distorter turn on.