一种高速ADC静态参数的内建自测试结构

针对混合信号电路的测试问题,提出了一种内建自测试(BIST)结构,分析并给出了如何利用该结构来计算片上高速模数转换器(ADC)的静态参数.该方法利用三角波信号作为测试激励,采用码密度直方图分析方法快速计算ADC的各静态参数.根据改进测试算法所构造的BIST结构实现了芯片内只有ADC电路的可测性设计,而不需要用到片内集成DSP.内嵌的信号发生器能自动生成高频连续三角波测试信号,适合高速ADC的测试.该BIST结构硬件开销小,易于片上集成,仿真试验表明了该结构的有效性.

A High-Speed BIST Architecture for ADC Parameters Testing

Aiming at the mixed-signal circuit testing,an integrated built-in self test(BIST) architecture for testing on-chip high speed ADC was presented.The static parameters of ADC were extracted from the histogram of ADC's out codes,which was stimulated with triangle-wave signal.The proposed on-chip signal generation provided accurate stimulant signals for high speed ADC testing,and the response analyzer calculated the parameters quickly with minimized circuits.The BIST has the advantages of high testing speed and low area overhead for easily integrated on chip.The results of simulation have proved the good performances of this architecture.