| Investigation of Improved Signal Process and Control Circuit for ColorPDP |
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| 引用本文： | 邱崧 仇润鹤 胡文静 张天桥 李煌. Investigation of Improved Signal Process and Control Circuit for ColorPDP[J]. 东华大学学报(英文版), 2007, 24(1): 94-98 |
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| 作者姓名： | 邱崧 仇润鹤 胡文静 张天桥 李煌 |
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| 作者单位： | [1]School of Information, Science ＆ Technology, East China Normal University, Shanghai 200062, China [2]College of Information Science and Technology, Donghua University, Shanghai 201620, China |
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| 基金项目： | The AM Foundation of Shanghai （No. 0206） |
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| 摘 要： | We present an alternative current-plasma display panel （AC-PDP） signal process and control circuit that fulfills the signal process and transform function. We proposed a novel driving logical waveform generator based on the SCI interface, which can real-time adjust the parameters to optimize performance of the PDP and facilitate the research and test. The use of nesting state-machine and parameterized design not only improves the resource utilization, but also makes it efficient and readable. The design has been written in synthesizable Verilog and fully verified using Xilinx FPGA device and applied in 42 - in AC- PDP module.
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| 关 键 词： | 交流等离子体显示屏 信号过程 控制电路 彩色显示器 |
| 文章编号： | 1672-5220（2007）01-0094-05 |
| 修稿时间： | 2006-07-26 |
Investigation of Improved Signal Process and Control Circuit for Color-PDP |
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| QIU Song,QIU Run-he,HU Wen-jing,ZHANG Tian-qiao,LI Huang. Investigation of Improved Signal Process and Control Circuit for Color-PDP[J]. Journal of Donghua University, 2007, 24(1): 94-98 |
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| Authors: | QIU Song QIU Run-he HU Wen-jing ZHANG Tian-qiao LI Huang |
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| Abstract: | We present an alternative current-plasma display panel (AC-PDP) signal process and control circuit that fulfills the signal process and transform function. We proposed a novel driving logical waveform generator based on the SCI interface, which can real-time adjust the parameters to optimize performance of the PDP and facilitate the research and test. The use of nesting state-machine and parameterized design not only improves the resource utilization, but also makes it efficient and readable. The design has been written in synthesizable Veriiog and fully verified using Xilinx FPGA device and applied in 42-in ACPDP module. |
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| Keywords: | AC-PDP Verilog SCI interface FPGA nesting State-Machine |
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