| 超前滞后型数字锁相环LL-DPLL在FPGA／CPLD中的实现 |
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| 引用本文： | 汪璇.超前滞后型数字锁相环LL-DPLL在FPGA／CPLD中的实现[J].湖北大学学报(自然科学版),2009,31(4):360-362. |
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| 作者姓名： | 汪璇 |
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| 作者单位： | 湖北大学知行学院计算机科学系; |
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| 摘 要： | 研究超前滞后型数字锁相环的系统原理．讨论了数字信号在3个功能模块超前滞后的原理，给出了它们在FPGA／CPLD中实现的方式，为需要全数字锁相环控制的设备提供了一种可行的电路设计方案．
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| 关 键 词： | 数字锁相环 FPGA/CPLD 数字鉴相器 数字环路滤波器 数控振荡器 |
Realization of LL-DPL in FPGA/CPLD |
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| WANG Xuan.Realization of LL-DPL in FPGA/CPLD[J].Journal of Hubei University(Natural Science Edition),2009,31(4):360-362. |
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| Authors: | WANG Xuan |
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| Institution: | School of Computer Science;Zhixing College of Hubei University;Wuhan 430011;China |
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| Abstract: | The systematic principle of lead-lag type digital phase locked loop was discussed.The lead-lag principles of three functional modules for digital signal were investigated,and the realization methods of different modules in FPGA/CPLD were given,which provided a fensible circuit design,for these facilities needing LL-DPLL. |
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| Keywords: | LL-DPL FPGA/CPLD DPD DLF DCO |
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