Efficiency of Cache Mechanism for Network Processors |
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Authors: | XU Bo CHANG Jian HUANG Shimeng XUE Yibo LI Jun |
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Institution: | aDepartment of Automation, Tsinghua University, Beijing 100084, China;bSchool of Software, Tsinghua University, Beijing 100084, China;cResearch Institute of Information Technology (RIIT), Tsinghua University, Beijing 100084, China;dTsinghua National Lab for Information Science and Technology, Beijing 100084, China |
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Abstract: | With the explosion of network bandwidth and the ever-changing requirements for diverse network-based applications, the traditional processing architectures, i.e., general purpose processor (GPP) and application specific integrated circuits (ASIC) cannot provide sufficient flexibility and high performance at the same time. Thus, the network processor (NP) has emerged as an alternative to meet these dual demands for today's network processing. The NP combines embedded multi-threaded cores with a rich memory hierarchy that can adapt to different networking circumstances when customized by the application developers. In today's NP architectures, multithreading prevails over cache mechanism, which has achieved great success in GPP to hide memory access latencies. This paper focuses on the efficiency of the cache mechanism in an NP. Theoretical timing models of packet processing are established for evaluating cache efficiency and experiments are performed based on real-life network backbone traces. Testing results show that an improvement of nearly 70% can be gained in throughput with assistance from the cache mechanism. Accordingly, the cache mechanism is still efficient and irreplaceable in network processing, despite the existing of multithreading. |
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Keywords: | cache network processor efficiency evaluation |
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