| 基于FPGA的计价器实验 |
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| 引用本文： | 傅晓程,张冶沁,刘芳.基于FPGA的计价器实验[J].实验科学与技术,2012,10(3):13-14,18. |
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| 作者姓名： | 傅晓程 张冶沁 刘芳 |
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| 作者单位： | 浙江大学电工电子实验中心,杭州,310058 |
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| 摘 要： | 由计价器的要求,提出设计方案,建立顶层文件;根据方案框图,设计各底层模块。通过在QuartusII8.1以及Modelsim软件中编译和下载测试,得到了仿真波形和关键设计结果。在DE0板Cyclone III系列EP3C16F484C6芯片上的下载测试,其多功能体现在不仅能实现显示乘车费用的功能,还可以通过选择键选择显示出乘车路程、乘客乘载时间以及等待时间。
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| 关 键 词： | 计价器 VHDL语言 算法 QuartusII8.1软件 |
FPGA Based Valuation Experiment |
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| FU Xiao-cheng,ZHANG Ye-qin,LIU Fang.FPGA Based Valuation Experiment[J].Experiment Science & Technology,2012,10(3):13-14,18. |
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| Authors: | FU Xiao-cheng ZHANG Ye-qin LIU Fang |
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| Institution: | (Electrical Engineering and Electronic Experiment Center, Zhejiang University, Hangzhou 310058, China) |
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| Abstract: | By the meter requirements, one puts forward the design plan and establishes the top file. According to the program diagram, one designs each module. In QuartusⅡ8. 1 and Modelsim software to compile and download test, the simulation waveforms and key design results can be obtained. In the DE0 board Cyclone Ⅲ series EP3C16F484C6 chip download test, its function is not only lie in realizing the display car cost function, also choose to select show＇s commute, passenger loading time and waiting time. |
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| Keywords: | valuation VHDL algorithm QuartusⅡ8 1 sfotuare |
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