| Tier1算法分析及其VLSI编解码复用结构设计 |
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| 作者单位： | 华南理工大学电子与信息学院 |
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| 摘 要： | 针对JPEG2000中Tier1编解码算法的复杂度高和硬件实现困难,提出一种Tier1编解码复用的VLSI体系结构。该结构改进了传统的位平面扫描方法和Tier1串行解码模式,充分利用了硬件资源,在通道并行处理的基础上实现编解码复用,具有很高的编解码效率和资源利用率。
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| 关 键 词： | Tier1 位平面编码 上下文 状态变量 码率控制 |
Common architecture for both Tier1 coding and decoding in JPEG2000 |
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| WU Zong-ze,ZHANG Xie,XIANG You-jun. Common architecture for both Tier1 coding and decoding in JPEG2000[J]. System Engineering and Electronics, 2008, 0(9) |
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| Authors: | WU Zong-ze ZHANG Xie XIANG You-jun |
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| Abstract: | Aiming at the complexity and difficulty for hardware implementation of the Tier1-coding in JPEG2000 system,a common architecture uniting encoder and decoder is presented.It improved the traditional bit-plane scanning technique and the Tier1's serial decoding mode for high-usage of circuit elements.Based on pass-parallel processing,this architecture has shared many hardware resources by multiplexing coding/decoding units,so as to reach high-speed and high elements-availablility ratio. |
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| Keywords: | Tier1 bit-plane encoding context state variable rate-control |
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