基于改进的电流传送器的模拟乘法器设计

为优化四象限模拟乘法器的电路性能, 以满足现代模拟信号处理电路高频低噪的应用要求, 提出了一种新 型低压四象限模拟乘法器。 该乘法器以基于改进的电流传送器(MDDCC: Modified Differential Difference Current Conveyor)的模拟平方器为基本电路, 采用台湾积体电路制造公司的 0. 18μm CMOS 工艺的 PSPICE(Personal Simulation Program with Integrated Circuit Emphasis)计算机软件进行仿真。 仿真结果表明, 该四象限乘法器具有良 好线性, 输入电压的范围为-0.1 V ~ +0.1 V, 截止频率为451.307 MHz, 当输入电压峰值为100 mV 时, 输出噪声 电压小于150 nV。 与已有乘法器比较, 该乘法器电路具有较好的线性特性以及较高的截止频率和带宽, 输出噪声 电压有所减少, 在高频信号处理系统中性能更优。

Four-Quadrant Multiplier Based on Modified Differential Difference Current Conveyor

In order to optimize the performance of four-quadrant analog multiplier, to meet the application requirements of modern analog signal processing circuit su ch as high-frequency and low-noise, a new low voltage four-quadrant analog mu ltiplier is proposed.The multiplier circuit uses the analog squarer based on MD DCC (Modified Differential Difference Current Conveyor) as a basic module.The f unction of multiplying circuit is confirmed by PSPICE (Personal Simulation Program with Integrated Circuit Emphasis) simulations using TSMC 0.18 μm CMOS technology.The proposed circuit has a good linearity.The range of input voltage is-0.1 V~+0.1 V, the-3 dB bandwidth of the proposed circuit is 451.307 MHz and the output noise voltage is less than 150 nV when the peak value of input voltage is 100 mV.By comparing with some available multipliers in ref erences, the proposed multiplier circuit has better linearity, higher cut-off f requency and reduces the output noise voltage.The four-quadrant analo g multiplier has good performance in the high frequency signal processing system.