| 基于时钟信号的异步时序逻辑电路设计 |
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| 引用本文： | 陈华,周家萍.基于时钟信号的异步时序逻辑电路设计[J].黔西南民族师范高等专科学校学报,2013(4):120-121. |
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| 作者姓名： | 陈华 周家萍 |
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| 作者单位： | 兴义民族师范学院,贵州兴义562400 |
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| 摘 要： | 与其他异步时序逻辑电路设计方法相比，基于时钟信号的设计法更简便、快捷。使用该方法时，不用画出时序图，直接从次态卡诺图中选定正确的时钟信号，再快速求出触发器状态方程。
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| 关 键 词： | 异步时序逻辑电路 时钟信号 次态卡诺图 |
Design of Asynchronous Sequential Logic Circuit Based on the Clock Signal |
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| Institution: | CHEN Hua ZHOU dia-Ping ( Xingyi Normal University for Nationalities, Xingyi Guizhou 562400, China) |
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| Abstract: | Compared with other asynchronous sequential logic circuit design method, design method based on the clock signal is more convenient, shortcut. The method is used, do not draw the timing diagram, select the correct clock signal directly from the states of Kano, and then to obtain rapidly trigger state equation. |
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| Keywords: | asynchronous sequential logic circuit clock signal next state Karnaugh map |
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