MFS结构铁电薄膜C-V特性的研究及界面电位降的计算

利用准分子激光原位淀积方法制备了BIT／PZT／BIT，PZT／BIT和BIT层状铁结构电薄膜，借助HP4192A低频率阻抗分析仪对样品的C—V特性进行了测试，用半导体理论讨论了金属—铁电薄膜—半导体（MFS）结构的电容电压（C—V）特性，由C-V曲线理论算出界面电位降Vi，结果表明，界面电位降与测量电容、薄膜电容及耗尽层电容有关．在三种结构中，BIT／PZT／BIT结构的界面电压降为最小，其界面效应优于单层和双层结构的界面效应．

Studies on the C-V characteristics and calculated of voltage drop at interfaces in MFS structure ferroelectric film

The multilayer ferroelectric films BIT/PZT/BIT,PZT/BI and BIT were prepared using scanning excimer laser.The HP4192A low frequency impedance apparatus was used to measure the C-V characteris curves of the samples.After discussed the capacity-voltage (C-V) characteristics of the metal-ferroelectric-semiconductor (MFS) structure using semiconductor theory and calculated the voltage trop at interface of the multilayer ferroelectric films.The results show that,the voltage trop of interface are related with the measured capacity,the capacity of ferroelectric films and the capacity of the depletion layer.The voltage trop at interface of the BIT/ PZT/BIT structure is the minimum among the three structures and its interface effect is better than the two others.