采用路选择技术实现的低功耗高速缓存设计

为了降低高速缓存的动态功耗,提出了一种路预测选择结构来降低传统的高速缓存的功耗。通过选择一路访问,而不是访问所有路高速缓存,使得功耗得到降低。同时,提出的路预测选择结构通过增加特定的标志寄存器,具备可配置功能,实现了路选择高速缓存和直接映射高速缓存之间的切换。实验结果表明:同传统的2路组相联高速缓存相比,采用路预测选择技术实现的高速缓存在访问期间的动态功耗降低约32%~40%,高速缓存缺失率基本相同。

Way selecting cache architecture for low power consumption

A prediction policy was developed for set-associative cache to achieve low power consumption by accessing only a single cache way,instead of accessing all the ways in a set with an additional one bit register,it also has the reconfigurable ability to be converted to one direct mapped cache for a specific application.Simulations show that the cache structure reduces dynamic power consumption up to 32%-40% over conventional 2-way set associative caches.The miss rate is almost the same as a conventional 2-way set associative cache.