整机性逻辑图自动生成中某些问题的解决方法

该逻辑图自动生成系统是ＶＨＤＬ语言高级逻辑综合系统中的一个子系统，它从高级逻辑综合的结果提取出网表信息作为输入．文中针对系统实现中遇到的一些问题，提出了具体的解决办法．讨论了自动布局中的定级算法、反馈环的处理及自动布线中的轨道分配等问题．通过对实例的测试，给出了测试结果和验证结论．

Solutions to Some Problems in the Automatic Generation of Systems Schematic Diagrams

This schematic diagram generation systerm is a sub-sytem of the VHDL language high-level logic synthesis system.It accepts the netlists abstracted from the result of logic synthesis as its input. In this paper, the level-assignment algorithm in automatic placement,the processing of feed-back loop and the track distribution in automatic routing are discussed. Some test results are given in the final part of thsi paper.