低功耗高集成度MP3解码器IP核设计

针对MP3解码器IP核低功耗和高集成度的要求,对MP3的解码算法和硬件结构进行优化,并设计定制处理单元高效率地执行解码运算,同时引入门控时钟实现MP3解码器的分时工作,从而以极低的硬件代价和功耗完成了MP3解码器IP核设计。该IP核采用16.384 MHz系统工作时钟,共耗用33 088个逻辑门和33 004字节存储单元,以0.18μm 1P4M CMOS工艺成功流片。芯片测试结果表明,该IP核具有正确的MP3解码功能,音质良好,最大解码功耗不超过9 mW,逻辑电路所占硅片面积仅为0.37 mm2。

ASIC design of a low-power high-integration MP3 decoder IP

This paper reports an ASIC implementation of MP3 decoder IP with low power consumption and high integration. The decoding algorithm and hardware structure are optimized to reduce the hardware cost. A customized process unit is designed to improve the overall computation efficiency. Gated clocks are arranged for power cycling to achieve extremely low power consumption. The MP3 decoder works at a system clock of 16.384 MHz and has been fabricated with 0.18 um 1P4M CMOS technology. It consumes 33088 logic gates and 33004 bytes RAM/ROM. Test result shows that the decoder works perfectly and consumes less than 9 mW, and the logic circuit occupies only 0.37 mm2 silicon areas.