| 并行DSP系统软件调试器设计与实现 |
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| 引用本文： | 吴琼之,南方,张峰.并行DSP系统软件调试器设计与实现[J].北京理工大学学报,2011,31(7):855-858. |
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| 作者姓名： | 吴琼之 南方 张峰 |
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| 作者单位： | 北京理工大学信息与电子学院,北京,100081 |
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| 摘 要： | 针对数字信号处理器(DSP)构成的专用并行处理系统的软件调试存在较多困难这一问题,提出了系统级调试的概念,在层次化总线硬件架构模型的基础上,讨论了系统软件调试的基本方法和任务,并采取层次化数据结构、静态符号表自动生成、可扩展底层接口等关键技术实现了一种专用多DSP系统调试工具.分析表明,此调试工具大大减轻了实时信号处理软件的调试工作量.
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| 关 键 词： | 并行处理 信号处理机 软件调试 |
| 收稿时间： | 2010/8/23 0:00:00 |
Implementation of a Parallel DSP System Debugger |
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| WU Qiong-zhi,NAN Fang and ZHANG Feng.Implementation of a Parallel DSP System Debugger[J].Journal of Beijing Institute of Technology(Natural Science Edition),2011,31(7):855-858. |
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| Authors: | WU Qiong-zhi NAN Fang and ZHANG Feng |
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| Institution: | School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China |
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| Abstract: | For the requirement that software debugging is quite difficult for dedicate parallel processing system consisting by multiple digital signal processor (DSP), concept of system-level debugging was proposed. The basic task and method of system-level debugging was discussed based on the hierarchical shared bus hardware structure model. A system level software debugger was designed and implemented with some key technology including hierarchical data structure, static symbol table auto-generation and extendable low level interface. This debugger makes it easy for system and global level debugging of large DSP processing array. |
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| Keywords: | parallel processing system signal processor software debugger |
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