| 一种高性能32位浮点乘法器的ASIC设计 |
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| 引用本文： | 赵忠武,陈禾,韩月秋.一种高性能32位浮点乘法器的ASIC设计[J].系统工程与电子技术,2004,26(4):531-534. |
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| 作者姓名： | 赵忠武 陈禾 韩月秋 |
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| 作者单位： | 北京理工大学电子工程系,北京,100081 |
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| 摘 要： | 介绍了一种32位浮点乘法器的ASIC设计。通过采用改进Booth编码的树状4:2列压缩结构,提高了乘法器的速度,降低了系统的功耗,且结构更规则,易于VLSI实现。整个设计采用VerilogHDL语言结构级描述,用TSMC0.25标准单元库进行逻辑综合。采用三级流水技术,完成一次32位浮点乘法的时间为28.98ns,系统的时钟频率可达103.52MHz。
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| 关 键 词： | 浮点乘法器 Booth编码 树状列压缩 |
| 文章编号： | 1001-506X(2004)04-0531-04 |
| 修稿时间： | 2003年2月24日 |
Design of high-performance 32-bit floating-point multipliers for ASIC |
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| ZHAO Zhong-wu,CHEN He,HAN Yue-qiu.Design of high-performance 32-bit floating-point multipliers for ASIC[J].System Engineering and Electronics,2004,26(4):531-534. |
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| Authors: | ZHAO Zhong-wu CHEN He HAN Yue-qiu |
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| Abstract: | A design of high-performance 32-bit floating-point multipliers for ASIC is presented. By using a structure of 4:2 column compression trees with the modified Booth encoding, the speed of the multipliers is improved and the power of the system is reduced. Furthermore, due to a more regular structure adopted, it is easy for VLSI realization of the multipliers. The whole design is described in Verilog HDL at structurelevel, and synthesized using the TSMC 0.25 standard cell library. With the technology of three-stage pipeline, 28.98ns is needed to complete a 32-bit floating-point multiplication, and the frequency of the system can reach 103.52MHz. |
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| Keywords: | Floating-point multiplier Booth encoding column compression tree |
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