基于Verilog的量程自转换数字频率计

本文运用Verilog语言,采用自顶向下的电子系统设计方法,在QuartusⅡ5.0软件环境下,将设计的数字频率计分为5个功能模块分别是分频模块、控制模块、计数模块、锁存模块和显示模块,然后将这五个模块一起生成最终的顶层文件,利用CPLD器件实现了量程自转换,测量精度较高,可以正确显示的数字频率计的设计。

An Adaptive Digital Frequency Meter Based on Verilog

In this paper, a designs of an adaptive digital frequency meter by using Verilog language and taking advantage of the top-down design approach was introduced. In the Quartus II 5.0 software environment,the digital frequency meter is divided into five functional modules which were the frequency module,control module,counting module,latch module and display module.Then it generated the final top-level files,and implemented automatic adjustment using CPLD devices.The measurement results showed a high accuracy.