| BESIII主触发系统VME机箱快控制插件的设计 |
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| 引用本文： | 司孝平,赵棣新,刘振安.BESIII主触发系统VME机箱快控制插件的设计[J].佳木斯大学学报,2006(2). |
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| 作者姓名： | 司孝平 赵棣新 刘振安 |
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| 作者单位： | 华北水利水电学院 河南郑州450011(司孝平)，中科院高能所 北京100039(赵棣新，刘振安) |
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| 摘 要： | 提出了“可预置计数限的计数逻辑”和“有暂停控制的双向计数器逻辑”,解决了VME总线主板所能处理的中断的频率与输入信号脉冲的频率不匹配的难题,消除了某些信号与系统时钟异步造成的准稳态;所设计的插件实现了VME总线程控流水线式发中断的功能.
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| 关 键 词： | VME总线 FPGA 仿真 |
Design of VME Crate Fast Control Board for BESIII Main Trigger System |
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| SI Xiao-ping,ZHAO Di-xin,LIU Zhen-an.Design of VME Crate Fast Control Board for BESIII Main Trigger System[J].Journal of Jiamusi University(Natural Science Edition),2006(2). |
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| Authors: | SI Xiao-ping ZHAO Di-xin LIU Zhen-an |
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| Institution: | SI Xiao-ping~1,ZHAO Di-xin~2,LIU Zhen-an~2 |
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| Abstract: | This paper introduces both "the counting logic with loadable port" and " the dual direction counting logic with pause port",which resolves the puzzle that the frequency of the interrupt dealed with by the VME master card couldn't match with that of the input signal pulse,and will avoid the uncertain state caused by the asynchronicm beteen some signals and the system clock signal.The board we designed can send out interrupt request to the VME master under control of the programs |
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| Keywords: | VME BUS FPGA simulation |
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