| FPGA数字脉冲压缩系统的研究与实现 |
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| 引用本文： | 贾广峰,付永庆,张旭.FPGA数字脉冲压缩系统的研究与实现[J].应用科技,2013(6):59-62. |
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| 作者姓名： | 贾广峰 付永庆 张旭 |
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| 作者单位： | 哈尔滨工程大学信息与通信工程学院,黑龙江哈尔滨150001 |
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| 基金项目： | 国家自然科学基金资助项目（60772025）. |
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| 摘 要： | 针对线性调频信号用FPGAIP核进行设计并实现了单通道的数字脉冲压缩系统．阐述了数字下变频、脉冲压缩的原理．介绍了系统的硬件结构、主要设计模块和在FPGA上实现对中频线性调频信号进行脉冲压缩处理的方法．最后给出了MATLAB仿真和FPGA硬件实验测试结果，验证了文中给出的数字脉冲压缩器设计的工程可行性．
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| 关 键 词： | 雷达 脉冲压缩 数字下变频 IP核 FPGA |
Research and realization on FPGA digital pulse compression system |
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| JIA Guangfeng,FU Yongqing,ZHANG Xu.Research and realization on FPGA digital pulse compression system[J].Applied Science and Technology,2013(6):59-62. |
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| Authors: | JIA Guangfeng FU Yongqing ZHANG Xu |
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| Institution: | College of Information and Communication Engineering, Harbin Engineering University, Harbin 150001, China |
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| Abstract: | A signal-channel digital pulse compression （DPC） system is implemented for the LFM signal and the DPC module is designed by using FPGA IP core. This paper describes the theory of digital down conversion and pulse com- pression, introduces the hardware structure and main design module of system, and the method on pulse compression for intermediate frequency LFM signal in FPGA. Finally, the authors give the testing results on MATALB simulation and FP- GA hardware experiment, demonstrating the engineering feasibility of the design on DPC system given in this paper. |
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| Keywords: | radar pulse compression digital down conversion IP core FPGA |
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