控制流综合子系统的研究与设计

本文论述了控制流综合技术的研究内容及研究背景,给出了 VHDL 高级综合系统 HLS/BIT 中控制流综合子系统的设计。该子系统通过 FSM 分解、状态化简、状态分配、组合逻辑划分、两级逻辑化简和多级逻辑综合等步骤完成综合任务,重点解决解题范围、优化和正确性问题。该子系统可望完成 RISC SPARC 一类复杂体系结构的计算机和 ASIC 的自动综合任务。

Research and Design of Control Stream Synthesis Subsystem

This paper discusses re.search contents and re.search backgrounds of control stream synthesis,and presents the design of the control stream synthesis subsystem in VHDL high -level synthesis system HLS/BIT.Through FSM decomposition,state minimization,state assignment,combinational logic partition,two -level logic minimization, and multiple -level logic synthesis,the subsystem implements its synthesis task to solve problems of scope,optimization and correctness.This subsystem can automatically synthesis computers and ASICs of complicated architecture similar to RISC SPARC.