| 时序逻辑电路的次态卡诺图综合设计法 |
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| 引用本文： | 唐昌凡.时序逻辑电路的次态卡诺图综合设计法[J].西华师范大学学报(哲学社会科学版),2000,21(3):296-300. |
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| 作者姓名： | 唐昌凡 |
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| 作者单位： | 四川师范学院计算机科学系!四川南充637002 |
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| 摘 要： | 时序逻辑电路的次态卡诺图综合设计法，是将有关信号的下降沿或上升沿用箭头在次态卡诺图中标示出来，并根据简要填出各约束的次态取值，从而将时钟信号的选取和自启动的检验合并在次态卡诺图中进行的１种新的设计方法。
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| 关 键 词： | 时序逻辑电路 次态卡诺图 综合设计法 |
Next-State Karnaugh Map comprehensive design of sequencial logic circuit |
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| TANG Chang,fan.Next-State Karnaugh Map comprehensive design of sequencial logic circuit[J].Journal of China West Normal University:Natural Science Edition,2000,21(3):296-300. |
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| Authors: | TANG Chang fan |
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| Abstract: | The Next-State Karnaugh Map comprehensive design is a new design.We use arrowheads to show the degressive and ascendant of the messages concerned in the Next-State Karnaugh Map and fill in with sub_cost of each restrained nape in needs of epitomization and so put the clock signal and the check of automotion together in the Next-State Karnaugh Map. |
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| Keywords: | sequential logic circuit Next_State Karnaugh Map comprehensive design clock signal |
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