一种基于蓝牙射频电路可测性设计的8位逐次逼近型ADC

介绍一种基于蓝牙射频电路可测性设计的8位逐次逼近型ADC.该电路的核心由采用rail-to-rail输入的比较器和R-2R网络结构的DAC组成.针对可测性设计的要求,电路结构简单紧凑,功耗低,芯片面积小.同时也提出,基于该ADC的一种适合于蓝牙射频电路的测试方法,通过该方法可以较好地对蓝牙射频电路的功能和性能进行监控和测试.芯片采用TSMC的0.35μm标准CMOS工艺制造,面积仅为0.15mm2.测试结果显示,在3.3V工作电压下,分辨率可达7位,且在高频工作环境下表现出很好的抗干扰特性.

An 8-bit Successive Approximation ADC Based on a Design for the Testability of the Bluetooth RF Circuit

This paper describes an 8-bit successive approximation ADC based on a design for the testability of the Bluetooth RF circuit. The ADC core is composed of a comparator with a rail-to-rail input range and a DAC with a R-2R structure. The main advantages of the ADC are that it is compact and simple in structure, low in power and small in the area, in this way it can meet the need of design for testability. Furthermore, a test method suitable for Bluetooth RF circuit based on the ADC is also presented. With this method, the function and performance of the Bluetooth RF circuit can be easily tested. The prototype was fabricated using 0.35 μm CMOS technology of TSMC. Its die area is only 0.15 mm~2. The measured results have shown that the circuit has more than 7 bit static resolution under 3.3 V supply voltage and good anti-interference performance in the high frequency has been achieved.