基于QR码构造的QC-LDPC码译码器设计与实现

基于平方剩余(quadratic residue,QR)码构造的准循环低密度奇偶校验(quasi cyclic low-density parity check,QC-LDPC)码的行重通常比较大，硬件实现时译码器消耗的资源也就较多。设计了一种在资源占用率和吞吐率方面较为平衡的部分并行结构的分层译码器。该译码器采用分层修正最小和算法(layered normalized min-sun algorithm, LNMSA)实现，利用部分并行结构同时处理层内连续n行；在变量节点后验概率信息的存储结构上，将连续的n个信息合并为1组，连续的2组采用2个随机存取存储器(random access memory, RAM)进行交替存储；在求取最小值和次小值时，将输入信息分为4组，再从4组中分别获取最小值比较出全局最小值和次小值，从而有效地降低了最小值和次小值比较运算的复杂度。在码长为2040、码率为0.83的码字和Xilinx Virtex-6开发板的测试环境下，译码器最大时钟频率可达166.7 MHz，吞吐量可达447.5 Mbit/s。

Design and implementation of QC-LDPC decoder based on QR code

The row weight of quasi cyclic low-density parity check (QC-LDPC) codes based on quadratic residue (QR) codes is usually large, which causes that the decoder will consume more resources on hardware implementation.Therefore,this paper designed a layered decoder based on partial-parallel structure compromised between resource occupancy and throughput. The decoder is implemented by the Layered Normalized Min-Sun Algorithm (LNMSA),which simultaneously processes consecutive n rows of a layer using a partial-parallel structure. On the storage structure of variable node posterior probability information, the continuous n information is combined into one group and the consecutive two groups are alternately stored by two random access memories(RAM). When obtaining the minimum value and the second small value, the input message is divided into 4 groups. Then, 4 minimum value are respectively computed from 4 groups and the global minimum value and second small value are obtained from them, which can effectively reduce the complexity of the comparison operation. In the test environment with code length of 2040, code rate of 0.83 and Xilinx Virtex-6 development board,the throughput of the decoder can reach 447.5 Mbit/s when working on 166.7 MHz.