应用于K波段分数分频频率综合器的多模分频器设计与优化

基于TSMC 90 nm CMOS工艺设计一款多模分频器，可以实现的分频比的范围为32~39.详细介绍了多模分频器的各部分模块，包括双模预定标器、S计数器和P计数器，分析并且讨论了P计数器加入与不加入重新定时电路的时序图.本文设计的分频器应用于K波段高速分数分频频率综合器.测试结果表明应用改进后的多模分频器，频率综合器的带内噪声可以优化15 dB，频偏10 kHz和频偏1 kHz的相位噪声可达到81.30 dBc/Hz和72.44 dBc/Hz. 

Design and Optimization of Multi-Modulus-Divider for K-Band Fractional-N Frequency Synthesizer

A multi-modulus-divider (MMD) was designed based on TSMC 90 nm CMOS process, achieving a division range of the MMD from 32 to 39. The block diagram of MMD, including double-modulus-divider, S counter and P counter were discussed in detail. Time sequence requirement of the P counters with and without retime circuit were analyzed and discussed. The proposed MMD was integrated into a K-band fractional-N frequency synthesizer. The measurement results show that in-band phase noise performance can be optimized about 15 dB through the modified MMD. The measurement results exhibit the phase noise performance can achieve -81.3 dBc/Hz and -72.44 dBc/Hz at 10 kHz frequency offset and 1 kHz frequency offset, respectively.