| 用FPGA实现高频时钟的分频和多路输出 |
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| 引用本文： | 赵传奇,苏明杰,吕英杰. 用FPGA实现高频时钟的分频和多路输出[J]. 中州大学学报, 2003, 20(1): 121-123 |
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| 作者姓名： | 赵传奇 苏明杰 吕英杰 |
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| 作者单位： | 郑州大学,物理工程学院,河南,郑州,450052 |
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| 摘 要： | FPGA(现场可编程逻辑门阵列)内部集成了四个全数字片内延时锁定环电路(Delay—Locked Loop，编写为DLL)，利用它能够实现对芯片输入时钟的零延时输出和时钟倍频，分频以及镜像操作等多种控制功能。本就是用DLL的功能来实现对64MHz的高频时钟的分频和多路输出。
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| 关 键 词： | FPGA 现场可编程逻辑门阵列 高频时钟 分频电路 多路输出 延时锁定环 频率综合 零延时 |
| 文章编号： | 1008-3715(2003)01-0121-03 |
| 修稿时间： | 2002-02-25 |
The Realization of Division and Multichannel Output of High-Frequency Clock Using the FPGA |
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| ZHAO Chuan-qi,SU Ming-jie,LV Ying-jie. The Realization of Division and Multichannel Output of High-Frequency Clock Using the FPGA[J]. Journal of Zhongzhou University, 2003, 20(1): 121-123 |
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| Authors: | ZHAO Chuan-qi SU Ming-jie LV Ying-jie |
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| Abstract: | FPGA provides four fully digital dedicated on-chip Delay-Locked Loop(DLL) circuits, Which provides zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits that improve and simplify system level design. |
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| Keywords: | FPGA DLL frequency synthesis zero propagation |
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