| 一种改进的双控制通路锁相环 |
| |
| 引用本文： | 宋颖,王源,贾嵩,刘志,赵宝瑛. 一种改进的双控制通路锁相环[J]. 北京大学学报(自然科学版), 2009, 45(4): 585 |
| |
| 作者姓名： | 宋颖 王源 贾嵩 刘志 赵宝瑛 |
| |
| 作者单位： | 北京大学微电子所，微电子器件与电路教育部重点实验室，北京100871；，E-mail：wangyuan@pku.edu.cn |
| |
| 摘 要： | 提出一种改进的双控制通路锁相环结构。改进锁相环的两个控制通路有不同的压控振荡器增益。其中, 粗调节通路的压控振荡器增益较大, 用来调节锁相环的输 出频率范围; 细调节通路的压控振荡器增益较小, 用来决定环路带宽, 同时优化锁相环的抖动特性。电路芯片采用SMIC 0. 18 μm CMOS Logic 工艺加工。后仿真结果表明该锁相环的输出频率范围为600 MHz到1. 6GHz, 并有良好的抖动特性。
|
| 关 键 词： | 锁相环 双控制通路 低抖动 |
| 收稿时间： | 2008-08-19 |
An Improved CMOS PLL with Dual Control Paths |
| |
| SONG Ying,WANG Yuan,JIA Song,LIU Zhi,ZHAO Baoying. An Improved CMOS PLL with Dual Control Paths[J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2009, 45(4): 585 |
| |
| Authors: | SONG Ying WANG Yuan JIA Song LIU Zhi ZHAO Baoying |
| |
| Affiliation: | Key Laboratory of Microelectronic Devices and Circuits, Ministry of Education , Institute of Microelectronics, Peking University, Beijing 100871; , E-mail: wangyuan@pku.edu.cn |
| |
| Abstract: | The authors propose an improved phased locked loop(PLL) architecture with dual control paths. The two control paths have different voltage controlled oscillator (VCO) gain. The coarse tuning path has a large VCO gain, and is used to cover operating frequency range. Having a small VCO gain, the fine tuning path determines the loop bandwidth and optimizes the jitter performance. This circuit is fabricated in a 0.18 μm CMOS logic process. The presented PLL has an output range from 600 MHz to 1.6 GHz, and exhibits good jitter characteristic. |
| |
| Keywords: | PLL dual control path low jitter |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
| 点击此处可从《北京大学学报(自然科学版)》浏览原始摘要信息 |
|
点击此处可从《北京大学学报(自然科学版)》下载全文 |
|
