一种有效降低扫描结构测试功耗的方法

提出了一种有效降低扫描测试功耗的设计方案.通过增加逻辑门结构来控制测试向量移入阶段扫描链上触发器翻转向组合逻辑电路的传播.同时,设计了时序优化算法以保持电路其他性能不发生大的改变.实验结果显示:通过采用ISCAS89基准测试程序进行分析,优化前无用动态功耗值约占总功耗的19.84%,优化后整体测试功耗降低约23%,有效地降低了无用动态功耗,并且此方案容易在已有的设计流程里实现.

An Effective Method for Depressing Scan-based Test Power

The scan-based testing method is often used to solve the problems of testing sequential logic, and its application is limited for the high-power operation characteristics. This paper proposed an effective scheme to reduce the scan-based test power to prevent the transitions of scan chains from reflecting into the combinational logic circuit lines by adding some logic gates. Then, we introduced an optimizational arithmetic ensuring other performances of the chip. The experiment results of ISCAS89 benchmark have shown that the useless dynamic power consumption accounts for about 19.84% of the total power consumption, while the overall test power consumption has been reduced by approximately 23% after optimization. This mechanism effectively reduces the unwanted dynamics power consumption, and it is easier to implement by means of the existing methods.