| 基于SystemVerilog的SoC功能验证方法研究 |
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| 引用本文： | 程刚,蔡敏.基于SystemVerilog的SoC功能验证方法研究[J].南京邮电大学学报(自然科学版),2009,9(22). |
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| 作者姓名： | 程刚 蔡敏 |
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| 作者单位： | 华南理工大学电子与信息学院,华南理工大学电子与信息学院 |
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| 摘 要： | 结合最新验证语言SystemVerilog的特点以及VMM（Verification Methodology Manual）验证架构，分别讨论了SoC设计过程中模块验证，集成验证和系统验证的一些改进措施，达到提高功能验证效率的目的。
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| 关 键 词： | SystemVerilog 单元验证 集成验证 系统验证 |
Research of SoC Functional Verification Based on SystemVerilog |
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| Cheng Gang and Cai Min.Research of SoC Functional Verification Based on SystemVerilog[J].Journal of Nanjing University of Posts and Telecommunications,2009,9(22). |
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| Authors: | Cheng Gang and Cai Min |
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| Institution: | School of Electronic and Information Engineering, South China University of Technology |
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| Abstract: | This paper basing on VMM and SystemVerilog which is a new verification language, introduces how to improve the efficiency of functional verification by modifying unit verification, integrated verification and system verification in SoC design process. |
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| Keywords: | ystemVerilog unit verification integrated verification system verification |
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