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基于微机的边界扫描测试主控系统的设计
引用本文:张华,陈朝阳,沈绪榜. 基于微机的边界扫描测试主控系统的设计[J]. 华中科技大学学报(自然科学版), 2002, 30(5): 22-24
作者姓名:张华  陈朝阳  沈绪榜
作者单位:华中科技大学图像识别与人工智能研究所,图像信息处理与智能控制教育部重点开放实验室
摘    要:分析了边界扫描测试技术的工作机制对测试主控系统的功能需求,提出了一种基于微机PCI总线的低成本边界扫描测试主控系统的硬件设计方案,该系统以PC机为平台,以用CPLD器件实现的JTAG主控器生成满足IEEE1149.1协议的边界扫描测试信号,并用普通的SRAM实现存存器共享,仿真表明,该系统产生的测试信号完全满足IEEE1149.1协议的时序要求,可用于IC和PCB的边界扫描测试,以及改进边界扫描测试的研究和实验。

关 键 词:边界扫描测试 JTAG主控器 集成电路测试 PCI CPLD
文章编号:1671-4512(2002)05-0022-03
修稿时间:2001-10-16

A PC-based boundary-scan testing system
Zhang Hua Chen Chaoyang Shen Xubang Postgraduate, Institute for Pattern Recognition , AI,Huazhong Univ. of Sci. and Tech.,Wuhan ,China.. A PC-based boundary-scan testing system[J]. JOURNAL OF HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY.NATURE SCIENCE, 2002, 30(5): 22-24
Authors:Zhang Hua Chen Chaoyang Shen Xubang Postgraduate   Institute for Pattern Recognition & AI  Huazhong Univ. of Sci.  Tech.  Wuhan   China.
Affiliation:Zhang Hua Chen Chaoyang Shen Xubang Postgraduate, Institute for Pattern Recognition & AI,Huazhong Univ. of Sci. and Tech.,Wuhan 430074,China.
Abstract:The mechanism of boundary scan test and the functional requirement of boundary scan tester are analyzed, and a PCI based boundary scan testing system is presented. In the system, PC works as a platform, the JTAG controller used to generate the boundary scan testing signals is realized by using CPLD chip, and normal SRAM chips is used as the shared memory. So the system is characterized by the whole function, convenience in using and low price. It can be used in the boundary scan testing of IC and PCB, as well as in the research and experiment of the technology.
Keywords:boundary scan test  JTAG controller  IC test  PCI  CPLD  
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