一种新型快速全数字锁相环的研究

提出了一种具有自动变模控制的快速全数字锁相环。该系统利用鉴相器的输出信号进行快捕区、慢捕区和锁定区的切换，并通过对数字环路滤波器的模数进行自动调节，来实现对环路带宽的实时控制。它能够有效地克服环路捕捉时间与抗噪声性能的矛盾。具有同步建立时间短、抗干扰能力强、静态相差小和易于集成等特点。该文介绍了该锁相环的原理和实现，并对其性能进行了分析和计算机仿真。

Research on a New Type of Fast All Digital Phase-Locked Loop

A fast all digital phase-locked loop with automatic modulus control is presented. It switches fast pull-in area, slow pull-in area and locking area by using the out signal of phase detector and controls the loop bandwidth by controlling the modulus of digital loop filter automatically. The system can overcome efficiently contradiction between pull-in time and anti-interference property. Its merits are that synchronization setting-up time is short, anti-interference ability is strong, static phase error is small and integration is easy. The work principle and implementation of DPLL is introduced. Its performances are analyzed and verified by simulation.