基于CORDIC算法的FPGA实现

在介绍传统的直接数字频率合成(DDS)技术和坐标旋转数字计算机(CORDIC)算法原理的基础上,就如何选择CORDIC算法的参数进行分析,并给出了推导过程。设计了一种基于高速并行流水线结构CORDIC算法的正弦信号发生器,在QuartusⅡ和Modelsim平台上综合和仿真表明,时钟频率可达205 MHz,误差在10-5数量级。给出了FPGA设计的具体过程,软件仿真结果和硬件应用结果。

Implementation of on FPGA Based on CORDIC Algorithm

Based on the introduction of the principles of the traditional Direct Digital frequency Synthesizer and CORDIC algorithm, the problem on how to choose the algorithm parameter is analyzed by detailed derivation. Then this paper describes a high-speed trigonometric signal generator with the parallel pipelined architecture of CORDIC. The study of Quartus compilation and Modelsim simulation shows the advantage with high clock frequency of 205 MHz and lower calculation errors of 10^-5. Finally, the implementation process on FPGA and the results of software simulation and hardware application were presented.